Workshop and Tutorial


Joint Program (HPCA-CGO-PPOPP-CC):
http://www.complang.tuwien.ac.at/hpca-cgo-ppopp-cc/program.html
http://www.complang.tuwien.ac.at/hpca-cgo-ppopp-cc/joint-program.pdf

Floor Plan: Link

Saturday Feb 24, 2018

AACBB: Accelerator Architecture in Computational Biology and Bioinformatics (Part1)
Room: Europa 3
HIPINEB: High-Performance Interconnection Networks in the Exascale and Big-Data Era (Part1)
Room: Europa 7
[08:30 - 08:40] Opening Remarks
[08:40 - 09:20] Keynote 1 - Onur Mutlu (ETH, CMU): "Accelerating Genome Analysis: A Primer on an Ongoing Journey"
[09:20 - 09:40] Mohammed Alser+, Hasan Hassan*, Akash Kumar&, Onur Mutlu* and Can Alkan+ (+Bilkent Univ., *ETH Zurich, &TU Dresden) Exploring Speed/Accuracy Trade-offs in Hardware Accelerated Pre-Alignment in Genome Analysis
[09:40 - 10:00] Lisa Wu, Frank Nothaft, Brendan Sweeney, David Bruns-Smith, Sagar Karandikar, Johnny Le, Howard Mao, Krste Asanovic, David Patterson and Anthony Joseph (UC Berkeley) Accelerating Duplicate Marking In The Cloud
[08:30 - 10:00] Opening
[08:45 - 10:00] Keynote: "The three L's in modern high-performance networking: Low latency, Low cost, Low processing load", Torsten Hoefler, ETH Zürich, Switzerland
[10:00 - 10:30] Coffee break
[10:30 - 11:10] Invited Talk - Bertil Schmidt (JGU Mainz): "Next Generation Sequencing: Big Data meets High Performance Computing Architectures"
[11:10 - 11:30] Wenqin Huangfu+, Zhenhua Zhu*, Tianqi Tang+, Xing Hu+, Yu Wang* and Yuan Xie+ (+UCSB, *Tsinghua University) GAME: GPU Acceleration of Metagenomics Clustering
[11:30 - 11:50] Jose M. Herruzo+, Sonia Gonzalez-Navarro+, Pablo Ibañez*, Victor Viñals*, Jesus Alastruey* and Oscar Plata+ (+Univ. of Malaga, *Univ. of Zaragoza) Exact Alignment with FM-index on the Intel Xeon Phi Knights Landing Processor
[11:50 - 12:10] Zheming Jin and Kazutomo Yoshii (ANL) Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment
[10:30 - 12:00] Technical Session 1 (research papers)
[12:00 - 13:30] Lunch
AACBB: Accelerator Architecture in Computational Biology and Bioinformatics (Part2)
Room: Europa 3
HIPINEB: High-Performance Interconnection Networks in the Exascale and Big-Data Era (Part2)
Room: Europa 7
[13:30 - 14:10] Keynote 2 - Srinivas Aluru (Georgia Tech): "Automata Processor and its Applications in Bioinformatics"
[14:10 - 14:30] Tommy Tracy Ii, Jack Wadden, Kevin Skadron and Mircea Stan (UVA) Streaming Gap-Aware Seed Alignment on the Cache Automaton
[14:30 - 14:50] Roman Kaplan, Leonid Yavits and Ran Ginosar (Technion) Processing-in-Storage Architecture for Large-Scale Biological Sequence Alignment
[14:50 - 15:10] Xueqi Li, Guangming Tan, Yuanrong Wang and Ninghui Sun (ICT) The Genomic Benchmark Suite: Characterization and Architecture Implications
[13:30 - 15:00] Technical Session 2 (research papers)
[15:00 - 15:30] Coffee break
[15:30 - 16:10] Invited Talk - Can Alkan (Bilkent University): "Addressing Computational Burden to Realize Precision Medicine"
[16:10 - 16:30] Sergiu Mosanu and Mircea Stan (UVA) Burrows-Wheeler Short Read Aligner on AWS EC2 F1
[16:30 - 16:50] Angélica Alejandra Serrano-Rubio, Amilcar Meneses-Viveros, Guillermo B. Morales-Luna and Mireya Paredes-López (CINVESTAV-IPN) Towards BIMAX: Binary Inclusion-MAXimal parallel implementation for gene expression analysis
[16:50 - 17:00] Short break
[17:00 - 17:15] Meysam Taassori+, Anirban Nag+, Keeton Hodgson+, Ali Shafiee* and Rajeev Balasubramonian+ (+Univ. of Utah, *Samsung Electronics) Memory: The Dominant Bottleneck in Genomic Workloads
[17:15 - 17:30] Meysam Roodi and Andreas Moshovos (Univ. of Toronto) Gene Sequencing: Where Time Goes
[17:30 - 17:45] Calvin Bulla, Lluc Alvarez and Miquel Moreto (BSC) Are Next-Generation HPC Systems Ready for Population-level Genomics Data Analytics?
[17:45 - 17:50] Closing remarks
[15:30 - 17:00] Panel Session: "Industrial perspective of high-speed communication technology evolution", moderated by Prof. Young Cho, University of Southern California
[18:15] Departure of the buses to the Heurigen
[18:30] Heurigen: Toni & Birgit Nigl (For more information please use this link.)

Sunday Feb 25, 2018

WP3: Second Workshop on Pioneering Processor Paradigms (Part1)
Room: Europa 5
Accelerating Big Data Processing with Hadoop, Spark and Memcached on Datacenters with Modern Architectures
Room: Europa 7
[08:30 - 08:40] Welcome and Introduction (Pradip Bose; on behalf of the workshop co-organizers: Ramon Bertran, Pradip Bose, Robert Montoye, John-David Wellman)
[08:40 - 09:40] Keynote-I: MICRO 2017 Test of Time Award, (Mikko H. Lipasti, University of Wisconsin - Madison)
[08:40 - 10:00] Retrospective Survey I, On the Evaluation of Computer Architectures, (Mario Badr and Natalie Enright Jerger, University of Toronto)
[08:30 - 10:00] Accelerating Big Data Processing... Session 1
[10:00 - 10:30] Coffee break
[10:30 - 11:20] Invited Talk: 40 years since dusk: will hardware capabilities finally make our systems more capable? (Lluis Vilanova, Technion)
[11:20 - 12:00] New/Exploratory paradigms, A Multi-component Branch Predictor Design for Low Resource Budget Processors (Moumita Das, Ansuman Banerjee and Bhaskar Sardar,Indian Statistical Institute and Jadavpur University)
FFT implementation using mono-instruction set computer architecture (Hiroki Shinba and Minoru Watanabe, Shizuoka University)
[10:30 - 12:00] Accelerating Big Data Processing... Session 2
[12:00 - 13:30] Lunch
WP3: Second Workshop on Pioneering Processor Paradigms (Part2)
Room: Europa 5
PULP: An open hardware platform, the story so far
Room: Europa 7
Turning HPC clusters into High Performance & High Throughput facilities by using remote GPU virtualization
Room: Pacific 2
[13:30 - 14:20] Keynote-II: TBD
[14:20 - 15:00] Restrospective Survey II, This Architecture Tastes Like Microarchitecture (Curtis Dunham and Jonathan Beard, ARM Research)
Project CrayOn: Back to the future for a more General-Purpose GPU? (Philip Machanick, Rhodes University)
[13:30 - 13:50] (Frank K. Gurkaynak) PULP concept and goals
[13:50 - 14:10] (Frank K. Gurkaynak) State of the art of open source hardware design
[14:10 - 14:30] (Frank K. Gurkaynak) Summary of PULP systems: PULP, PULPino, PULPissimo
[14:30 - 15:00] (Florian Zaruba) PULP cores: OR10N, RI5CY, Zero-riscy, Ariane
[13:30 - 15:00]
[Session 1.1] Presentation of remote GPU virtualization techniques and rCUDA features (50 minutes)
[Session 1.2] Practical demonstration about how to install and use rCUDA (40 minutes)
[15:00 - 15:30] Coffee break
[15:30 - 16:30] Panel Session
[16:30 - 17:00] Discussion driven by workshop organizers
[15:30 - 16:00] (Francesco Conti) Advanced PULP silicon implementations
[16:30 - 17:00] (Francesco Conti) Acceleration for PULP systems, examples from cryptography and neural networks
[17:00 - 17:30] (Andreas Kurth) PULP Programming
[15:30 - 17:00]
[Session 2] Guided exercises so that the audience uses rCUDA in a cluster located at Technical University of Valencia, Spain
Time for attendees to freely exercise with rCUDA in the remote cluster (a set of exercises is proposed)
[18:00] HPCA/CGO/PPoPP Welcome Reception and Poster Session
[19:45] Women-in-Computer-Architecture (WICARCH) get-together (Anthony's Bar)